瑞芯微RV1126B_HDK(20250613) PCB参考图纸和通用说明文档等

手机开发 · 发表于 2026-10-15 14:42

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由于PCB原理图等资料太多份了。所以就不每个截图了。下面把文件列表给大家列出来。如果有需要的在这。
全部资料一起打包了。

瑞芯微RV1126B_HDK(20250613).rar

40.8 MB, 下载次数: 11, 下载积分：金币 -5 枚

01_Common Document\RV1126&RV1126B-P Differences Description and Compatibility Design Notes(兼容设计说明)
01_Common Document\RV1126B-P_Package_PinLength_V1.0_20250318_EN.xlsx
01_Common Document\RV1126B-P_PinOut_V1.0_20250519_EN.xlsx
01_Common Document\RV1126B_EVB1_User_Guide_V1.0_20250613_CN.pdf
01_Common Document\RV1126B_Methods_for_Processing_Unused_Pins_V1.0_20250606_EN.xlsx
01_Common Document\RV1126B_Package_PinLength_V1.0_20250318_EN.xlsx
01_Common Document\RV1126B_PinOut_V1.1_20250519_EN.xlsx
01_Common Document\RV1126B_Power_Consumption_Test_Report_V1.0_20250527_CN.xlsx
01_Common Document\RV1126&RV1126B-P Differences Description and Compatibility Design Notes(兼容设计说明)\RV1126&RV1126B-P_Differences_Description_and_Compatibility_Design_Notes_V1.26_20250604_CN&EN.pdf
01_Common Document\RV1126&RV1126B-P Differences Description and Compatibility Design Notes(兼容设计说明)\RV1126&RV1126B_Function_Mapping_Table_V1.0_20250527.xlsx
01_Common Document\RV1126&RV1126B-P Differences Description and Compatibility Design Notes(兼容设计说明)\瑞芯微RV1126&RV1109替换RV1126B-P说明_V1.0_20250416.pdf
02_DDR Template\RV1126B_Template_DDR3P216DD4_37x30_1066MHz_H1R6
02_DDR Template\RV1126B_Template_DDR3P216SD4_38x30_1066MHz_H1R6
02_DDR Template\RV1126B_Template_DDR4P216DD4_32x38_1333MHz_H1R6
02_DDR Template\RV1126B_Template_DDR4P216SD4_30x40_1333MHz_H1R6
02_DDR Template\RV1126B_Template_LP4XD200P132SD6146_31X21_1333MHz_H1R6
02_DDR Template\RV1126B_Template_LP4XD200P132SD81468_28x18_1333MHz_H1R2
02_DDR Template\RV1126B_Template_DDR3P216DD4_37x30_1066MHz_H1R6\V10_20250611
02_DDR Template\RV1126B_Template_DDR3P216DD4_37x30_1066MHz_H1R6\V10_20250611\Allegro.jrl
02_DDR Template\RV1126B_Template_DDR3P216DD4_37x30_1066MHz_H1R6\V10_20250611\RV1126B_Template_DDR3P216DD4_37x30_1066MHz_H1R6_V10_20250611.brd
02_DDR Template\RV1126B_Template_DDR3P216DD4_37x30_1066MHz_H1R6\V10_20250611\RV1126B_Template_DDR3P216DD4_37x30_1066MHz_H1R6_v10_20250611.DSN
02_DDR Template\RV1126B_Template_DDR3P216DD4_37x30_1066MHz_H1R6\V10_20250611\RV1126B_Template_DDR3P216DD4_37x30_1066MHz_H1R6_v10_20250611.pdf
02_DDR Template\RV1126B_Template_DDR3P216DD4_37x30_1066MHz_H1R6\V10_20250611\RV1126B_Template_DDR3P216DD4_37x30_1066MHz_H1R6_v10_20250611核心板设计重点说明.doc
02_DDR Template\RV1126B_Template_DDR3P216DD4_37x30_1066MHz_H1R6\V10_20250611\RV1126B_Template_DDR3P216DD4_37x30_1066MHz_H1R6_V10_20250611阻抗叠层.xls
02_DDR Template\RV1126B_Template_DDR3P216SD4_38x30_1066MHz_H1R6\V10_20250609
02_DDR Template\RV1126B_Template_DDR3P216SD4_38x30_1066MHz_H1R6\V10_20250609\RV1126B_Template_DDR3P216SD4_38x30_1066MHz_H1R6_V10_20250609.BRD
02_DDR Template\RV1126B_Template_DDR3P216SD4_38x30_1066MHz_H1R6\V10_20250609\RV1126B_Template_DDR3P216SD4_38x30_1066MHz_H1R6_V10_20250609.DSN
02_DDR Template\RV1126B_Template_DDR3P216SD4_38x30_1066MHz_H1R6\V10_20250609\RV1126B_Template_DDR3P216SD4_38x30_1066MHz_H1R6_V10_20250609.pdf
02_DDR Template\RV1126B_Template_DDR3P216SD4_38x30_1066MHz_H1R6\V10_20250609\RV1126B_Template_DDR3P216SD4_38x30_1066MHz_H1R6_V10_20250609核心板设计重点说明.doc
02_DDR Template\RV1126B_Template_DDR3P216SD4_38x30_1066MHz_H1R6\V10_20250609\RV1126B_Template_DDR3P216SD4_38x30_1066MHz_H1R6_V10_20250609阻抗叠层.xls
02_DDR Template\RV1126B_Template_DDR4P216DD4_32x38_1333MHz_H1R6\V10_20250611
02_DDR Template\RV1126B_Template_DDR4P216DD4_32x38_1333MHz_H1R6\V10_20250611\RV1126B_Template_DDR4P216DD4_32x38_1333MHz_H1R6_V10_20250611.brd
02_DDR Template\RV1126B_Template_DDR4P216DD4_32x38_1333MHz_H1R6\V10_20250611\RV1126B_Template_DDR4P216DD4_32x38_1333MHz_H1R6_V10_20250611.DSN
02_DDR Template\RV1126B_Template_DDR4P216DD4_32x38_1333MHz_H1R6\V10_20250611\RV1126B_Template_DDR4P216DD4_32x38_1333MHz_H1R6_V10_20250611.pdf
02_DDR Template\RV1126B_Template_DDR4P216DD4_32x38_1333MHz_H1R6\V10_20250611\RV1126B_Template_DDR4P216DD4_32x38_1333MHz_H1R6_V10_20250611核心板设计重点说明.doc
02_DDR Template\RV1126B_Template_DDR4P216SD4_30x40_1333MHz_H1R6\V10_20250522
02_DDR Template\RV1126B_Template_DDR4P216SD4_30x40_1333MHz_H1R6\V10_20250522\RV1126B_Template_DDR4P216SD4_30x40_1333MHz_H1R6_V10_20250522.brd
02_DDR Template\RV1126B_Template_DDR4P216SD4_30x40_1333MHz_H1R6\V10_20250522\RV1126B_Template_DDR4P216SD4_30x40_1333MHz_H1R6_V10_20250522.DSN
02_DDR Template\RV1126B_Template_DDR4P216SD4_30x40_1333MHz_H1R6\V10_20250522\RV1126B_Template_DDR4P216SD4_30x40_1333MHz_H1R6_V10_20250522.pcb
02_DDR Template\RV1126B_Template_DDR4P216SD4_30x40_1333MHz_H1R6\V10_20250522\RV1126B_Template_DDR4P216SD4_30x40_1333MHz_H1R6_V10_20250522.pdf
02_DDR Template\RV1126B_Template_DDR4P216SD4_30x40_1333MHz_H1R6\V10_20250522\RV1126B_Template_DDR4P216SD4_30x40_1333MHz_H1R6_V10_20250522核心板设计重点说明.doc
02_DDR Template\RV1126B_Template_DDR4P216SD4_30x40_1333MHz_H1R6\V10_20250522\RV1126B_Template_DDR4P216SD4_30x40_1333MHz_H1R6_V10_20250522阻抗叠层.xls
02_DDR Template\RV1126B_Template_LP4XD200P132SD6146_31X21_1333MHz_H1R6\V10_20250425
02_DDR Template\RV1126B_Template_LP4XD200P132SD6146_31X21_1333MHz_H1R6\V10_20250425\Allegro.jrl
02_DDR Template\RV1126B_Template_LP4XD200P132SD6146_31X21_1333MHz_H1R6\V10_20250425\Allegro.jrl,1
02_DDR Template\RV1126B_Template_LP4XD200P132SD6146_31X21_1333MHz_H1R6\V10_20250425\RV1126B_Template_LP4XD200P132SD6146_31X21_1333MHz_H1R6_V10_20250425.brd
02_DDR Template\RV1126B_Template_LP4XD200P132SD6146_31X21_1333MHz_H1R6\V10_20250425\RV1126B_Template_LP4XD200P132SD6146_31X21_1333MHz_H1R6_V10_20250425.DSN
02_DDR Template\RV1126B_Template_LP4XD200P132SD6146_31X21_1333MHz_H1R6\V10_20250425\RV1126B_Template_LP4XD200P132SD6146_31X21_1333MHz_H1R6_V10_20250425.pdf
02_DDR Template\RV1126B_Template_LP4XD200P132SD6146_31X21_1333MHz_H1R6\V10_20250425\RV1126B_Template_LP4XD200P132SD6146_31X21_1333MHz_H1R6_V10_20250425核心板设计重点说明.doc
02_DDR Template\RV1126B_Template_LP4XD200P132SD6146_31X21_1333MHz_H1R6\V10_20250425\RV1126B_Template_LP4XD200P132SD6146_31X21_1333MHz_H1R6_V10_20250425阻抗叠层.xls
02_DDR Template\RV1126B_Template_LP4XD200P132SD81468_28x18_1333MHz_H1R2\V10_20250425
02_DDR Template\RV1126B_Template_LP4XD200P132SD81468_28x18_1333MHz_H1R2\V10_20250425\allegro.jrl
02_DDR Template\RV1126B_Template_LP4XD200P132SD81468_28x18_1333MHz_H1R2\V10_20250425\allegro.jrl,1
02_DDR Template\RV1126B_Template_LP4XD200P132SD81468_28x18_1333MHz_H1R2\V10_20250425\RV1126B_Template_LP4XD200P132SD81468_28x18_1333MHz_H1R2_V10_20250425.brd
02_DDR Template\RV1126B_Template_LP4XD200P132SD81468_28x18_1333MHz_H1R2\V10_20250425\RV1126B_Template_LP4XD200P132SD81468_28x18_1333MHz_H1R2_V10_20250425.brd.lck
02_DDR Template\RV1126B_Template_LP4XD200P132SD81468_28x18_1333MHz_H1R2\V10_20250425\RV1126B_Template_LP4XD200P132SD81468_28x18_1333MHz_H1R2_V10_20250425.DSN
02_DDR Template\RV1126B_Template_LP4XD200P132SD81468_28x18_1333MHz_H1R2\V10_20250425\RV1126B_Template_LP4XD200P132SD81468_28x18_1333MHz_H1R2_V10_20250425.pdf
02_DDR Template\RV1126B_Template_LP4XD200P132SD81468_28x18_1333MHz_H1R2\V10_20250425\RV1126B_Template_LP4XD200P132SD81468_28x18_1333MHz_H1R2_V10_20250425核心板设计重点说明.doc
02_DDR Template\RV1126B_Template_LP4XD200P132SD81468_28x18_1333MHz_H1R2\V10_20250425\RV1126B_Template_LP4XD200P132SD81468_28x18_1333MHz_H1R2_V10_20250425阻抗叠层.xls
03_Product Line Branch(AI-IPC)\01_Product Document
03_Product Line Branch(AI-IPC)\02_Key Device Specifications
03_Product Line Branch(AI-IPC)\03_Reference Design
03_Product Line Branch(AI-IPC)\RV1126B(AI-IPC)Hardware_Document_Release_Note_and_File_List_V10_20250606.xlsx
03_Product Line Branch(AI-IPC)\03_Reference Design\V10_20250527
03_Product Line Branch(AI-IPC)\03_Reference Design\V10_20250527\PCB Library Ver1.0
03_Product Line Branch(AI-IPC)\03_Reference Design\V10_20250527\SCH Library Ver1.0
03_Product Line Branch(AI-IPC)\03_Reference Design\V10_20250527\SCH Ver1.0
03_Product Line Branch(AI-IPC)\03_Reference Design\V10_20250527\PCB Library Ver1.0\BGA491_14R0x14R0x1R00.psm
03_Product Line Branch(AI-IPC)\03_Reference Design\V10_20250527\SCH Library Ver1.0\RK801-2.OLB
03_Product Line Branch(AI-IPC)\03_Reference Design\V10_20250527\SCH Library Ver1.0\RV1126B-P.OLB
03_Product Line Branch(AI-IPC)\03_Reference Design\V10_20250527\SCH Library Ver1.0\RV1126B.OLB
03_Product Line Branch(AI-IPC)\03_Reference Design\V10_20250527\SCH Ver1.0\RV1126B_AI-IPC_REF_SCH_V10_20250606.DSN
03_Product Line Branch(AI-IPC)\03_Reference Design\V10_20250527\SCH Ver1.0\RV1126B_AI-IPC_REF_SCH_V10_20250606.pdf
04_Product Line Branch(BAT-IPC)\01_Product Document
04_Product Line Branch(BAT-IPC)\02_Key Device Specifications
04_Product Line Branch(BAT-IPC)\03_Reference Design
04_Product Line Branch(BAT-IPC)\03_Reference Design\PCB Library Ver1.0
04_Product Line Branch(BAT-IPC)\03_Reference Design\SCH Ver.Beta
04_Product Line Branch(BAT-IPC)\03_Reference Design\PCB Library Ver1.0\RV1126B_BGA491_14R0X14R0X1R00-LP4X200ball.pcb
04_Product Line Branch(BAT-IPC)\03_Reference Design\SCH Ver.Beta\RV1126B_BAT-IPC_REF_SCH_Beta_20250207.DSN
04_Product Line Branch(BAT-IPC)\03_Reference Design\SCH Ver.Beta\RV1126B_BAT-IPC_REF_SCH_Beta_20250207.pdf
05_Product Line Branch(AOV-IPC)\01_Product Document
05_Product Line Branch(AOV-IPC)\02_Key Device Specifications
05_Product Line Branch(AOV-IPC)\03_Reference Design
05_Product Line Branch(AOV-IPC)\03_Reference Design\PCB Library Ver1.0
05_Product Line Branch(AOV-IPC)\03_Reference Design\SCH Ver.Beta
05_Product Line Branch(AOV-IPC)\03_Reference Design\PCB Library Ver1.0\BGA491_14R0X14R0X1R00.dra
05_Product Line Branch(AOV-IPC)\03_Reference Design\PCB Library Ver1.0\RK801_qfn28_p40_4r00x4r00x0r80_t.pcb
05_Product Line Branch(AOV-IPC)\03_Reference Design\SCH Ver.Beta\RV1126B_AOV_IPC_REF_SCH_BETA_20250320.DSN
05_Product Line Branch(AOV-IPC)\03_Reference Design\SCH Ver.Beta\RV1126B_AOV_IPC_REF_SCH_BETA_20250320.pdf